Micron reveals flash roadmap for over 500 3D NAND layers – Blocks and Files

Micron has 232-layer 3D NAND in development and a roadmap for over 500 layers.

3D NAND is made by layering groups of cells on top of each other in a vertical stack. The more layers in a flash array, the higher the capacity. All manufacturers are currently building chips over 100 layers with higher layer counts in sight.

Yesterday, Western Digital revealed that it was building a 162-layer NAND with a 200+ layer chip coming soon.

Micron unveiled details of its NAND and DRAM roadmap at an Investor Day event on May 12. end of the 2022 calendar.

A slide provided a number of staged layers increases to level 500 and above, but without a time scale:

Double-stacked technology refers to the stacking of two 3D NAND dies on top of each other, known as “chain stacking”. This overcomes semiconductor manufacturing difficulties such as etching through the layers as the number of layers increases. The sides of these holes can warp as the depth of the hole deepens and prevent NAND cells from working properly.

Micron said it was focusing on QLC (4bits/cell) NAND and did not mention increasing the cell bit count to 5 with PLC (penta level cell), which Western Digital is investigating and Soldigm developed. We think it’s because Micron is being cautious, not because it dismissed NAND PLC as unworkable.

Here is a table comparing the status, history and plans of 3D NAND overlay of NAND manufacturers:

NAND including Micron
the manufacturing start dates are approximate

WD would say there is no inherent superiority in having a slightly higher layer count – 238 (SK hynix), 232 versus 212, for example – as it reduces its cell size laterally, widthwise and length, while increasing the height of the matrix by adding layers. The combination of the two techniques means it can increase matrix density to the same degree or more than its competitors and have fewer layers.

There is an implicit advantage here because building a layer means doing a bunch of processing steps and, all things being equal, doing 232 processing groups takes longer than doing 212. But so many others things come into play, such as the manufacturing yield of the wafers, than the end result; manufacturing cost, chip density price, endurance and performance are not only based on the number of manufacturing steps.

Micron claims that its 232-layer technology represents the most advanced NAND in the world:

Micron CuA
CuA = CMOS under board

This slide showed a 1TB (128TB) TLC array. Micron didn’t mention zoned SSDs in his presentation, but he did talk about external controllers, involving NAND/SSD controllers running in the host system, which is necessary with zoned SSDs. We might expect to see SSDs using 232-layer NAND shipping in late 2023.

Investor Day did not cover storage-class memory, such as 3D XPoint, which it used to manufacture for Intel. But he was talking about CXL (Computer eXpress Link) and a slide showed something called Emerging Memory Technology at the end of a CXL link:

micron slide

Another spoke of “new memory architecture” and “the CXL roadmap focused on customer co-invention”, whatever that might mean. This could involve possible customer specific CXL related memory devices. We believe the emerging memory and new memory architecture could apply to storage-class memory and/or 3D DRAM.

Solidigm, Western Digital and Micron’s NAND roadmaps attest to the technological health and vitality of the NAND and SSD markets, meaning we can expect growing flash data storage capacity and speed of increased application.

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