New Ways to Shrink: Further EUV Scaling Depends on Breakthroughs in Materials Engineering and Metrology


A brief history of 2D scaling

Traditional Moore’s Law 2D scaling has defined the chip industry’s technology roadmap for more than half a century.

In the era of Dennard scaling up to around 2000, we reduced the size of transistors by 50% every two years. We shrunk the gate that controls the on-off state of the transistor, and its length defined the node: 90 nm, 65 nm, etc. We scaled the gate oxide proportionally, and chipmakers enjoyed simultaneous improvements in performance, power, and area cost or “PPAC.” Looking back, progress was easy!

Between 2000 and 2010, gate length and gate oxide scaling reached limits: we could model smaller features, but not without physical issues such as gate leakage and contact resistance that negated the performance and power benefits of reduced area cost. We switched to “equivalent scaling” in which the gate length remained at around 30 nm and the physical scaling of the gate oxide is blocked. Node names were no longer tied to actual dimensions. Instead, by using materials engineering techniques like strained silicon and high-K metal gates, we’ve allowed the benefits of ‘PP’ to continue even when scaling up.” AC” slowed down. From 2010, the 3D FinFET architecture arrived to enable further advancements in both PP and AC.

Materials engineering also helped when the lithography stalled at 193 nm limiting single pass immersion to around 80 nm. Dual configuration and quadrature allowed further scaling at 40 nm and 20 nm steps, respectively.

EUV simplifies configuration but complicates wiring

EUV arrived in time for the 5 nm node, enabling a 25 nm pitch setup in a single step. However, new materials engineering techniques were needed to make EUV practical. For example, the contact vias of transistors configured at the resolution limits of EUV are difficult to fill with metal using traditional coating-and-fill barrier methods: the remaining area for metal wiring is so small that the contact resistance increases exponentially. Integrated material solutions enabled selective contact deposition, eliminating coating barriers and producing wide, low-resistance contacts.

New ways to shrink

Are there new ways to reduce even more? Yes, actually there are two.

As one of our major customers explained, continuous intrinsic scaling, i.e. classic 2D Moore’s Law, provides about half the improvement in node logic density. 3nm. The other half comes from co-optimization of design technology – DTCO – which refers to clever rearrangements of logic cell elements to reduce cell area to a constant lithographic pitch.

During our Master Class on April 21, I will discuss how we can further scale using EUV-if we can solve the growing challenges in materials engineering and metrology that I will describe in a moment. During our Master Class on May 26*, we will provide the technical details of Rear Power Distribution Networks, an innovative and emerging DTCO technique that increases logic density independent of lithography pitch.

Materials Engineering Challenges for Further EUV Scaling

Producing photons using EUV technology is difficult and expensive. As a result, we need to run EUV lithography using 10 times fewer photons than with deep UV. Also, the patterns we create with EUV, such as alternating lines and spaces, are much narrower. As a result, EUV photoresists are much thinner. The thinness allows us to develop the photomask patterns with fewer photons and helps prevent narrow patterns from collapsing into each other.

Issue 1: Correcting Stochastic Errors in EUV Photoresists

In fact, because the number of photons and the thickness of the resin are limited, we encounter “stochastic errors” which are imperfections in the lines and spaces that we model in the photoresist. The smaller the EUV models, the larger the stochastic errors as a proportion of the device characteristics. If these irregularities are transferred to the wafer, they can lead to misconfigurations, such as gaps in the lines that cause open circuits; bridges between adjacent lines that cause short circuits; and the misalignment of features in adjacent layers of the chip – called edge placement errors – that reduce yield.

What we need is a breakthrough in materials engineering that can manipulate EUV photoresist patterns to correct stochastic errors and prevent them from being transferred to the wafer.

Problem 2: Reduce the cost of EUV modeling

Chip designers already want to create patterns even narrower than the resolution limits of EUV. Designers can split tight patterns in half so that half of the pattern is deposited using a first EUV pass and the other half is deposited in a second step. But the extra EUV step adds considerable cost. What we need is a new technology that can gently spread EUV patterns on the photoresist to create incredibly tight spacing after a single EUV pass.

Problem 3: Increase the accuracy of EUV modeling films

I explained that EUV photoresist is very thin and delicate. Therefore, we have to deposit several layers of material between the photoresist and the wafer before etching the desired pattern:

A transfer layer quickly receives the pattern from the EUV photomask, before the etching completely erodes the photoresist. Beneath the transfer layer is a hard mask: this receives the pattern and is more resistant, withstanding the longer etch times required to reproduce the pattern in the wafer. There may actually be more than one hard mask layer.

Traditionally, spin deposition and films are used to form the transfer layer and hard mask. Films start out as a liquid and are inherently soft. Spin deposition also presents uniformity issues. The continued scaling up of EUV requires a new approach.

Problem 4: Ensure photoresist pattern fidelity before etching the slices

Optical layering tools are used to center the EUV patterns on the wafer before we commit to etching. eBeam CD SEM tools are used to complete centering and, more importantly, to measure critical dimensions of photoresist patterns before etching them into the wafer. The traditional energies of the CD SEM eBeam can alter the photoresist, potentially distorting the patterns. Traditional CD SEM image resolution struggles to discern ever finer EUV patterns. My colleagues in our eBeam metrology division are working on a new system to address these challenges.

Issue 5: Fixed edge placement errors

The chips are made one layer at a time. Each layer can contain billions of individual features, such as lines, line segments, and vias. The edges of each of these features should line up properly with their opposing features on the layers above and below. If features are misaligned, there can be subtle errors that affect power and performance, or large errors that can ruin entire wafers or a large percentage of the chips on each wafer. The resulting time-to-market and yield issues are becoming increasingly difficult to resolve as we continue to scale back with EUV.

Traditional optical layering aligns the different layers using “proxy targets” that are placed in non-active areas of the wafer, such as the scribe lines between chips that are sawn off during chip separation. In theory, aligning these marks, one layer at a time, correctly aligns all of the billions of feature edges on all of the chip’s critical layers.

In practice, the individual features we try to align are at least 10 times smaller than the proxy targets. Additionally, the subtle variability inherent in lithography as well as process steps such as deposition and etching create subtle issues, such as pitch walking, that cannot be seen and controlled using optical techniques.

Increasingly, lithography experts are using eBeam technology to scan each 2D layer and identify pattern variations. However, their efforts are still largely focused on diagnosing problems one 2D layer at a time and making optical adjustments when the next chip layer is scanned. As we continue to evolve using EUV, engineers encounter more and more “blind spots”: they go out of their way using optical corrections and still end up with edge placement errors that they can’t solve. Additionally, if a pattern excursion occurs during high-volume manufacturing, engineers relying on the proxy target approximation can waste weeks of time and production waiting for new masks.

What the industry needs is 3D imaging and pattern control that directly images and measures critical features across multiple layers of the chip simultaneously to quickly characterize and diagnose all sources of error edge placement, including layering and alignment; uniformity of line and cut; roughness of lines and cut edges; and pitch walking.

Number 6: Use Big Data and AI to Accelerate Progress

To accelerate R&D and ramp up high-volume production, we should ideally get big data and use advanced analytics to unravel the various contributors to patterning issues. We would use this data to create optimized process recipes with the widest margins, called process windows, to enable intrinsic scaling with EUV to continue long into the future. I invite you to listen to our Master classto learn more about how we can use sensors, metrology, and analytics to accelerate process R&D, accelerate the scale-up of new process technologies, and benefit from higher yields over time life of a new process technology. We will also cover the five other materials engineering and metrology problems that I have described in this blog.

*Expected date

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